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description agilents INA-31063 is a silicon rfic amplifier that has excellent gain and isolation for applications to 2.5 ghz. packaged in an ultra- miniature sot-363 package, it requires half the board space of a sot-143 package. the INA-31063 uses a unique circuit topology that provides broadband gain and 50 w input and 200 w output impedance. with more than 35 db of isolation to 2.5 ghz makes it an excellent candidate for lo buffer applications. the INA-31063 is fabricated using hps 30 ghz f max isosat tm silicon bipolar process which uses nitride self-alignment, submicrometer lithography, trench isolation, ion implantation, and polyimide intermetal dielec- tric and scratch protection to achieve superior performance, uniformity, and reliability. dc C 2.5 ghz 3 v, high isolation silicon rfic amplifier technical data INA-31063 surface mount sot-363 (sc-70) package pin connections and package marking simplified schematic output & v d gnd 1 31 gnd 2 gnd 1 input 1 2 3 6 5 4v d note: package marking provides orientation and identification. features ? high reverse isolation -40 db at 1.9 ghz ? single +3v supply ? 15 db |s 21 | 2 at 1.9 ghz ? 200 w output impedance ? ultra-miniature package ? unconditionally stable applications ? lo buffer and amplifier for cellular, cordless, special mobile radio, pcs, ism, wireless lan, dbs, tvro, and tv tuner input v d output & v d gnd1 gnd2
2 thermal resistance [2] : q jc = 170 c/w notes: 1. operation of this device above any one of these limits may cause permanent damage. 2. t c = 25 c (t c is defined to be the temperature at the package pins where contact is made to the circuit board) INA-31063 electrical specifications , t c = 25 c, z o = 50 w ,v d = 3 v symbol parameters and test conditions units min. typ. max. std. dev. [4] |s 21 | 2 gain in 50 w system f = 0.9 ghz db 14.0 f = 1.9 ghz 13.0 [3] 15.1 0.44 f = 2.4 ghz 15.0 nf 50 noise figure f = 1.9 ghz db 6.1 0.25 p 1db output power at 1 db gain compression f = 0.9 ghz dbm -1.8 f = 1.9 ghz -2.1 f = 2.4 ghz -3.5 ip 3 output third order intercept point f = 0.9 ghz dbm 9.1 f = 1.9 ghz 8.5 f = 2.4 ghz 6.8 vswr in input vswr f = 0.1 C 2.4 ghz 1.35:1 vswr out output vswr f = 0.1 C 2.4 ghz 3.5:1 i d device current ma 11.0 13.5 [3] 0.47 notes: 3. guaranteed specifications are 100% tested in production. 4. standard deviation number is based on measurement of a large number of parts from three non-consecutive wafer lots during the initial characterization of this product, and is intended to be used as an estimate for distribution of the typical specification. absolute maximum ratings absolute symbol parameter units maximum [1] v d device voltage, v 6.0 output to ground p in cw rf input power dbm +7.0 t j junction temperature c 150 t stg storage temperature c -65 to 150
3 INA-31063 typical performance, t c = 25 c, z o = 50 w , v d = 3 v 0 20 10 15 5 0 1.0 0.5 1.5 2.0 2.5 gain (db) frequency (ghz) figure 1. gain vs. frequency and voltage measured in a 50 system. noise figure (db) frequency (ghz) figure 2. noise figure vs. frequency and voltage. p 1 db (dbm) frequency (ghz) figure 3. output power for 1 db gain compression vs. frequency and voltage. gain (db) frequency (ghz) figure 4. gain vs. frequency and temperature measured in a 50 system. noise figure (db) frequency (ghz) figure 5. noise figure vs. frequency and temperature. figure 6. output power for 1 db gain compression vs. frequency and temperature. 2.7 v 3.0 v 3.3 v 0 20 10 15 5 0 1.0 0.5 1.5 2.0 2.5 -40 c +25 c +85 c 4.5 7.5 5.5 6.5 5 0 1.0 0.5 1.5 2.0 2.5 7 6 2.7 v 3.0 v 3.3 v -8 4 -4 0 -6 0 1.0 0.5 1.5 2.0 2.5 2 -2 2.7 v 3.0 v 3.3 v p 1 db (dbm) frequency (ghz) -8 4 -4 0 -6 0 1.0 0.5 1.5 2.0 2.5 2 -2 -40 c +25 c +85 c vswr frequency (ghz) figure 7. input and output vswr vs. frequency. 0 4 2 3 1 0 1.0 0.5 1.5 2.0 2.5 vswr in vswr out i d (ma) v d (v) figure 8. supply current vs. voltage and temperature. 0 25 10 15 5 02 1345 20 4 8 6 7 5 0 1.0 0.5 1.5 2.0 2.5 -40 c +25 c +85 c -40 c +25 c +85 c figure 9. third order intercept point, ip 3 vs. frequency and temperature. ip 3 (dbm) frequency (ghz) 2 14 6 10 4 0 1.0 0.5 1.5 2.0 2.5 12 8 -40 c +25 c +85 c
4 INA-31063 typical scattering parameters [5] , t c = 25 c, z o = 50 w ,v d = 3.0 v freq. s 11 s 21 s 12 s 22 k ghz mag ang db mag ang db mag ang mag ang factor 0.1 0.14 171 13.6 4.81 -5 -32.5 0.024 10 0.49 -3 3.45 0.2 0.15 167 13.7 4.84 -11 -37.1 0.014 11 0.52 -4 5.37 0.3 0.14 164 13.7 4.83 -15 -36.0 0.016 -3 0.51 -4 4.79 0.4 0.15 163 13.7 4.86 -20 -37.6 0.013 -39 0.54 -3 5.60 0.5 0.15 152 13.8 4.88 -26 -39.8 0.010 -6 0.53 -5 7.31 0.6 0.14 152 13.8 4.88 -30 -37.1 0.014 -18 0.51 -5 5.38 0.7 0.14 151 13.9 4.93 -35 -38.6 0.012 -35 0.53 -5 6.02 0.8 0.15 147 14.0 4.99 -40 -41.3 0.009 -46 0.55 -8 7.66 0.9 0.14 143 14.0 5.04 -45 -45.5 0.005 -35 0.56 -11 13.54 1.0 0.14 138 14.1 5.06 -51 -45.2 0.005 -4 0.55 -14 13.71 1.1 0.14 137 14.2 5.12 -56 -44.1 0.006 -6 0.54 -17 11.32 1.2 0.13 136 14.3 5.20 -61 -45.3 0.005 -16 0.55 -19 13.20 1.3 0.13 132 14.4 5.26 -67 -47.3 0.004 20 0.55 -24 16.34 1.4 0.13 129 14.5 5.33 -73 -46.8 0.005 40 0.55 -28 12.92 1.5 0.13 125 14.6 5.34 -80 -41.9 0.008 58 0.53 -35 8.32 1.6 0.12 128 14.6 5.36 -85 -41.5 0.008 30 0.49 -36 8.84 1.7 0.12 130 14.8 5.49 -91 -44.3 0.006 27 0.50 -37 11.23 1.8 0.12 130 14.9 5.57 -97 -45.0 0.006 31 0.50 -40 11.18 1.9 0.12 130 15.1 5.69 -104 -46.4 0.005 53 0.51 -44 12.80 2.0 0.11 128 15.2 5.77 -111 -45.8 0.005 61 0.52 -48 12.59 2.1 0.10 129 15.3 5.83 -119 -44.7 0.006 74 0.53 -54 10.20 2.2 0.08 130 15.3 5.79 -127 -43.4 0.007 78 0.52 -62 8.94 2.3 0.07 134 15.1 5.71 -135 -42.4 0.008 79 0.50 -68 8.22 2.4 0.05 144 15.0 5.63 -143 -41.7 0.008 76 0.49 -73 8.42 2.5 0.04 166 14.8 5.50 -152 -41.8 0.008 74 0.49 -80 8.64 2.6 0.04 -176 14.5 5.29 -160 -42.2 0.008 76 0.47 -87 9.24 2.7 0.05 -159 14.1 5.06 -167 -43.2 0.007 77 0.44 -93 11.43 2.8 0.06 -151 13.7 4.84 -174 -43.1 0.007 85 0.40 -97 12.34 2.9 0.08 -149 13.3 4.62 178 -43.3 0.007 86 0.39 -100 13.10 3.0 0.10 -150 12.8 4.36 172 -44.2 0.006 96 0.36 -105 16.46 3.1 0.13 -152 12.3 4.11 165 -44.0 0.006 105 0.34 -108 17.71 3.2 0.15 -153 11.8 3.89 159 -43.0 0.007 115 0.32 -109 16.22 3.3 0.17 -155 11.3 3.65 153 -42.0 0.008 118 0.30 -111 15.17 3.4 0.19 -158 10.7 3.42 147 -42.2 0.008 125 0.29 -113 16.23 3.5 0.21 -160 10.1 3.20 142 -41.3 0.009 139 0.27 -115 15.49 3.6 0.22 -161 9.6 3.02 137 -38.9 0.011 143 0.25 -114 13.50 3.7 0.24 -163 9.1 2.84 132 -38.0 0.013 144 0.24 -114 12.09 3.8 0.25 -165 8.5 2.66 128 -37.3 0.014 151 0.23 -115 12.00 3.9 0.25 -167 8.0 2.51 124 -35.5 0.017 155 0.21 -113 10.55 4.0 0.26 -169 7.5 2.37 120 -34.2 0.019 153 0.21 -111 9.98 4.1 0.27 -172 7.0 2.24 116 -33.2 0.022 153 0.20 -109 9.10 4.2 0.27 -175 6.5 2.12 112 -32.4 0.024 154 0.20 -108 8.83 4.3 0.28 -178 6.1 2.01 109 -31.3 0.027 154 0.19 -105 8.26 4.4 0.29 180 5.6 1.90 105 -30.5 0.030 154 0.19 -103 7.82 4.5 0.29 177 5.1 1.81 102 -29.7 0.033 153 0.19 -101 7.47 4.6 0.30 174 4.7 1.72 98 -28.9 0.036 152 0.19 -99 7.17 4.7 0.31 171 4.3 1.63 95 -28.3 0.039 151 0.19 -98 6.94 4.8 0.32 169 3.8 1.55 92 -27.7 0.041 151 0.19 -97 6.89 4.9 0.33 166 3.4 1.48 89 -27.0 0.045 151 0.19 -95 6.54 5.0 0.33 164 3.0 1.41 87 -26.2 0.049 150 0.19 -93 6.30 note: 5. reference plane per figure 19 in applications information section.
5 INA-31063 applications information introduction the INA-31063 is a +3 volt silicon rfic amplifier that is designed with a two stage internal network to provide a broadband gain and 50 w input and 200 w output impedance. with a p -l db com- pressed output power of -3 dbm and high isolation of 40 db, the INA-31063 is well suited for lo buffer amplifier applications in mobile communication systems. the 200 w output impedance of the amplifier allows easy connec- tions to additional rfics and some filters. in addition to use in buffer applications in the cellular market, the INA-31063 will find many applications in battery operated wireless communication systems. operating details the INA-31063 is a voltage biased device that operates from a +3 volt power supply with a typical current drain of 11 ma. all bias regulation circuitry is integrated into the rfic. figure 10 shows a typical imple- mentation of the INA-31063. the supply voltage for the INA-31063 must be applied to two terminals, the v d pin and the rf output pin. rf output rf input v d c bypass c out c block 31 rfc gnd2 gnd1 gnd1 figure 10. basic amplifier application. the v d connection to the ampli- fier is rf bypassed by placing a capacitor to ground near the v d pin of the amplifier package. the power supply connection to the rf output pin is achieved by means of a rf choke (inductor). the value of the rf choke must be large relative to 50 w in order to prevent loading of the rf output. the supply voltage end of the rf choke is bypassed to ground with a capacitor. if the physical layout permits, this can be the same bypass capacitor that is used at the v d terminal of the amplifier. blocking capacitors are normally placed in series with the rf input and the rf output to isolate the dc voltages on these pins from circuits adjacent to the amplifier. the values for the blocking and bypass capacitors are selected to provide a reac- tance at the lowest frequency of operation that is small relative to 50 w . since the gain of the INA-31063 extends down to dc, the frequency response of the amplifier is limited only by the values of the capacitors and choke. rf layout an example for the rf layout for the INA-31063 is shown in figure 11. rf output and v d gnd 1 gnd 1 gnd 2 50 50 figure 11. rf layout this example uses a microstripline design (solid groundplane on the backside of the circuit board). the circuit board material is 0.031-inch thick fr4. plated through holes (vias) are used to bring the ground to the top side of the circuit where needed. the performance of INA-31063 is sensitive to ground path inductance. the two-stage design creates the possibility of a feedback loop being formed through the ground returns of the stages, gnd 1 and gnd 2. gnd 1 gnd 2 via figure 12. INA-31063 potential ground loop. gnd 1 gnd 2 via via figure 13. INA-31063 suggested layout. at least one ground via should be placed adjacent to each ground pin to assure good rf grounding. multiple vias are used to reduce the inductance of the path to ground and should be placed as close to the package terminals as practical. the effects of the potential ground loop shown in figure 12 may be observed as a peaking in the gain versus frequency response, an increase in input vswr, or even as return gain at the input of the INA-31063.
6 figure 14 shows an assembled 50 w amplifier. the +3 volt supply is fed directly into the v d pin of the INA-31063 and into the rf output pin through the rf choke (rfc). capacitor c3 provides rf bypassing for both the v d pin and the power supply end of the rfc. capacitor c4 is optional and may be used to add additional bypassing for the v d line. a well- bypassed v d line is especially necessary in cascades of ampli- fier stages to prevent oscillation that may occur as a result of rf feedback through the power supply lines. 900 mhz 50 w matched example the use of a simple impedance matching network will typically increase both gain and output power by 1.5 db and 1.5 dbm, respectively. the values that were chosen for the two tuning ele- ments were a 12 nf series induc- tor and a 1.0 pf shunt capacitor. the rf choke was a 56 nh (coilcraft 1008cs-221, toko ll2012-f or equivalent). the two blocking capacitors were 100 pf and the bypass capacitor was 1000 pf. rf output rf input v d c bypass c out c block c shunt 31 rfc rfm figure 15. impedance matched output amplifier circuit. these values provide excellent amplifier performance at 900 mhz. larger values for the choke and capacitors can be used to extend the lower end of the bandwidth. a convenient method for making rf connection to the demonstration board is to use a pcb mounting type of sma connector (johnson 142-0701881, or equivalent). these connectors can be slipped over the edge of the pcb and the center conductor soldered to the input and output lines. the ground pins of the connectors can be soldered to the ground plane on the backside of board. frequency rfc rfm c shunt 400 m hz 120 nh 27 nh 2.7 pf 900 mhz 56 nh 12 nh 1.0 pf 1900 mhz 33 nh 4.7 nh none 2400 mhz 27 nh 1.8 nh none figure 16. suggested matching elements for common frequency bands. the test results for the INA-31063 were measured on the 50 w input and output impedance matched amplifier described above. p out (dbm) p in (dbm) -16 4 -8 -12 -30 -20 -25 -10 -15 -5 0 0 -4 900 mhz 1900 mhz figure 17. measured input power vs. output power on assembled 50 w amplifier at 900 mhz and 1900 mhz. an important specification when selecting a lo buffer amplifier is reverse isolation under p 1db input conditions. figure 18 shows the measured reverse isolation with -10 dbm applied to the input of the device. -60 -20 -40 -30 -50 0 1.0 0.5 1.5 2.0 2.5 reverse isolation (db) frequency (ghz) figure 18. measured isolation. c2 rfc c1 ctune ltune c3 c4 v d ina-3xx63 demo board 31 figure 14. assembled amplifier.
7 pcb materials typical choices for pcb material for low cost wireless applications are fr-4 or g-10 with a thickness of 0.025 (0.636 mm) or 0.031 inches (0.787 mm). a thickness of 0.062 inches (1.574 mm) is the maximum that is recommended for use with this particular device. the use of a thicker board material increases the inductance of the plated through vias used for rf grounding and may deteriorate circuit performance. adequate grounding is needed not only to obtain maximum amplifier performance but also to reduce any possibility of instability. phase reference planes the positions of the reference planes used to measure s-parameters for this device are shown in figure 19. as seen in the illustration, the reference planes are located at the point where the package leads contact the test circuit. reference planes test circuit figure 19. phase reference planes. sot-363 pcb layout the INA-31063 is packaged in the miniature sot-363 (sc-70) surface mount package. a pcb pad layout for the sot-363 package is shown in figure 20 (dimensions are in inches). this layout provides ample allowance for package placement by auto- mated assembly equipment without adding pad parasitics that could impair the high frequency performance of the INA-31063 the layout that is shown with a nominal sot-363 package foot- print superimposed on the pcb pads for reference. 0.026 0.075 0.016 0.035 figure 20. pcb pad layout for INA-31063 (dimensions in inches). statistical parameters several categories of parameters appear within this data sheet. parameters may be described with values that are either minimum or maximum, typi- cal, or standard deviations. the values for parameters are based on comprehensive product characterization data, in which automated measurements are made on a large number of parts taken from 3 non-consecutive process lots of semiconductor wafers. the data derived from product characterization tends to be normally distributed, e.g., fits the standard bell curve. param- eters considered to be the most important to system performance are bounded by minimum or maximum values. for the INA-31063, these parameters are: power gain ( |s21| 2 ), and the device current (i d ). each of these guaranteed parameters is 100% tested. values for most of the parameters in the table of electri- cal specifications that are de- scribed by typical data are the mathematical mean ( m ), of the normal distribution taken from the characterization data. for parameters where measurements or mathematical averaging may not be practical, such as s-parameters or noise param- eters and the performance curves, the data represents a nominal part taken from the center of the characterization distribution. typical values are intended to be used as a basis for electrical design. to assist designers in optimizing not only the immediate circuit using the INA-31063, but to also optimize and evaluate trade-offs that affect a complete wireless system, the standard deviation ( s ) is provided for three of the electrical specifications param- eters (at 25 c) in addition to the mean. the standard deviation is a measure of the variability about the mean. it will be recalled that a normal distribution is completely described by the mean and standard deviation. standard statistics tables or calculations provide the probability of a parameter falling between any two values, usually symmetrically located about the mean. referring to figure 21 for example, the probability of a parameter being between 1 s is 68.3%; between 2 s is 95.4%; and between 3 s is 99.7%. 68% 95% 99% parameter value mean ( ), typ -3 s -2 s -1 s +1 s +2 s +3 s figure 21. normal distribution.
8 smt assembly reliable assembly of surface mount components is a complex process that involves many material, process, and equipment factors, including: method of heating (e.g., ir or vapor phase reflow, wave soldering, etc.) circuit board material, conductor thickness and pattern, type of solder alloy, and the thermal conductivity and thermal mass of components. components with a low mass, such as the sot-363 package, will reach solder reflow temperatures faster than those with a greater mass. the INA-31063 has been qualified to the time-temperature profile shown in figure 22. this profile is representative of an ir reflow type of surface mount assembly process. after ramping up from room temperature, the circuit board with components attached to it (held in place with solder paste) passes through one or more preheat zones. the preheat zones increase the temperature of the board and components to prevent thermal shock and begin evaporating solvents from the solder paste. the reflow zone briefly elevates the temperature sufficiently to produce a reflow of the solder. the rates of change of tempera- ture for the ramp-up and cool down zones are chosen to be low enough to not cause deformation of the board or damage to compo- nents due to thermal shock. these parameters are typical for a surface mount assembly process for the INA-31063. as a general guideline, the circuit board and components should only be exposed to the minimum temperatures and times necessary to achieve a uniform reflow of solder. for more information on mount- ing considerations for packaged microwave semiconductors, please refer to agilent application note an-a006. electrostatic sensitivity rfics are electrostatic discharge (esd) sensitive devices. although the INA-31063 is robust in design, permanent damage may occur to these devices if they are sub- jected to high-energy electrostatic discharges. electrostatic charges as high as several thousand volts (which readily accumulate on the human body and on test equip- ment) can discharge without degradation in performance, reliability, or failure. electronic devices may be subjected to esd damage in any of the following areas: ? storage & handling ? inspection & testing ? assembly ? in-circuit use the INA-31063 is an esd class 1 device. therefore, proper esd precautions are recommended when handling, inspecting, testing, assembling, and using these devices to avoid damage. for more information on electro- static discharge and control refer to agilent application note an- a004r. time (seconds) t max temperature ( c) 0 0 50 100 150 200 250 60 preheat zone cool down zone reflow zone 120 180 240 300 figure 22. surface mount assembly profile.
9 package dimensions outline 63 (sot-363/sc-70) INA-31063 part number ordering information part number devices per container container INA-31063-blk 100 tape strip in antistatic bag INA-31063-tr1 3,000 7" reel INA-31063-tr2 10,000 13" reel 2.20 (0.087) 2.00 (0.079) 1.35 (0.053) 1.15 (0.045) 1.30 (0.051) ref. 0.650 bsc (0.025) 2.20 (0.087) 1.80 (0.071) 0.10 (0.004) 0.00 (0.00) 0.25 (0.010) 0.15 (0.006) 1.00 (0.039) 0.80 (0.031) 0.20 (0.008) 0.10 (0.004) 0.30 (0.012) 0.10 (0.004) 0.30 ref. 10 0.425 (0.017) typ. dimensions are in millimeters (inches)
10 tape dimensions and product orientation for outline 63 p p 0 p 2 f w c d 1 d e a 0 8 max. t 1 (carrier tape thickness) t t (cover tape thickness) 5 max. b 0 k 0 description symbol size (mm) size (inches) length width depth pitch bottom hole diameter a 0 b 0 k 0 p d 1 2.24 0.10 2.34 0.10 1.22 0.10 4.00 0.10 1.00 + 0.25 0.088 0.004 0.092 0.004 0.048 0.004 0.157 0.004 0.039 + 0.010 cavity diameter pitch position d p 0 e 1.55 0.05 4.00 0.10 1.75 0.10 0.061 0.002 0.157 0.004 0.069 0.004 perforation width thickness w t 1 8.00 0.30 0.255 0.013 0.315 0.012 0.010 0.0005 carrier tape cavity to perforation (width direction) cavity to perforation (length direction) f p 2 3.50 0.05 2.00 0.05 0.138 0.002 0.079 0.002 distance width tape thickness c t t 5.4 0.10 0.062 0.001 0.205 0.004 0.0025 0.00004 cover tape 31 31
www.semiconductor.agilent.com data subject to change. copyright ? 1999 agilent technologies obsoletes 5967-5770e 5968-1238e (11/99)

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